1. Field of the Invention
The present invention generally relates to integrated circuit memories and, more particularly, to the formation of a plate for trench storage capacitors particularly as used in dynamic random access memories (DRAMs).
2. Description of the Prior Art
Basic and indispensable operations of digital data processing circuits involve the ability to fetch one or more sequences of digital signal bits from memory, perform an operation thereon and return the result to storage. Therefore, memory structures from which signals can be accessed and to which signals can be stored in a cycle time comparable to an operating cycle of the processing circuit have been required. To answer this requirement random access memories of both static and dynamic types have been developed and their respective designs continually refined over the years.
Recent advances in digital data processing circuits has greatly increased requirements for large capacity and improved functionality of storage which may be rapidly accessed by the processing circuitry in cycle times which have become extremely short. Dynamic random access memories have generally been used to answer the requirement of increased storage capacity since data is stored therein as charge on a capacitor which can be fabricated at extremely small size and in very large numbers on a single semiconductor chip. A well-known and widely used capacitor structure occupying an extremely small area on a chip is known as a trench capacitor which, in a basic form includes a capacitor dielectric and an electrode, as one capacitor plate, formed within a blind aperture (often oval in plan view) generally referred to as a trench, in a substrate; using a region within the substrate as the second capacitor plate common to the trench capacitors on the chip.
As is understood by those skilled in the art, storage or retrieval of signals is achieved in modern, high-capacity DRAMs by the storage of very small amounts of charge. Stored charge is also subject to leakage and must be periodically refreshed in order to avoid corruption of data and while the amount of stored charge remains sufficient to provide rapid and reliable response of sense amplifiers, generally by a "read and write back" combination of operations for each cell and which can be performed simultaneously or concurrently in parallel in different partitions of memory.
The speed with which writing can be done at a given voltage depends, to a large degree, on the parasitic series resistance of the memory cell capacitors. Therefore, it is often desirable to form a structure of enhanced conductivity to serve as a common capacitor plate for the memory cells on a chip or in a partition thereof. Such structures may also facilitate isolation of cells from mutual parasitic coupling effects. As a further refinement, as memory cells have become more densely integrated on a chip, applying a bias to such a conductive structure approximating a voltage mid-way between the logic signal levels allows reduction of electrical field and stress on the capacitor dielectric which can thus be made thinner. Reduction of the dielectric thickness, consistent with the levels of electrical stress which must be tolerated, increases capacitance of each trench capacitor and potential amount of charge storage at a given voltage and allows the "footprint" of each capacitor to be reduced. In view of the number of memory cells which can currently be fabricated on a chip, seemingly slight reductions in cell footprint can provide substantial chip space for further memory cells, so-called peripheral circuits for increased memory functionality and redundant circuits to increase manufacturing yield.
Some of the read, write and refresh operations as well as differentiation between partitions of memory can be facilitated by biasing the electrode which forms a common capacitor plate for a plurality of capacitors. Particularly as to differentiation between partitions, if partitions are provided, separate and mutually isolated common electrodes must be provided which, of course, cannot be done if the substrate forms a common electrode for all storage capacitors on the chip. Additionally, the extent of any such electrode must be readily determinable as an incident of chip design in order to avoid interference with other circuitry provided on the chip to allow access to memory cells and to store and recover data, such as address decoders, sense amplifiers and peripheral circuits.
Therefore, in recent DRAM designs, a separate, independently biasable electrode has been included by a buried doped region within the substrate, such as an n-type region within a p-type substrate and beneath a p-well provided for the capacitor array so that the electrode provided by the buried, doped region will surround the capacitor portion of each trench. (Generally an isolation or other region is formed at the bottom of the trench and some portion of the upper regions of the trench may include transistors or other circuit elements or portions thereof used for accessing a particular capacitor of a memory cell.)
Such buried electrodes have been formed in known DRAM designs, such as that disclosed in U.S. Pat. No. 5,264,716 to Donald M. Kenney and assigned to the assignee of the present invention and which is hereby fully incorporated by reference, by out-diffusion of plate dopant from a diffusion source within the trench, thereby assuring that the doped region so formed will surround the capacitor portion of the trench. However, the process steps required for forming an electrode in this manner involve deposition of the dopant source, masking the vertical dopant profile and removal of the dopant source by etching, These operations involve substantial process complexity and have been found to have a substantial adverse impact on manufacturing yield.
An alternative method involves the use of an n-type substrate into which a p-type surface implantation is made prior to etching of trenches. However, while avoiding process complexity, this approach introduces some additional problems and is subject to some severe operational limitations. Specifically, the low noise and high latch-up resistance of n-well CMOS logic circuitry are sacrificed, a new latch-up mechanism is presented by the necessary p-n-p-n vertical path, the freedom to bias the plate arbitrarily is eliminated, and costs of n-type wafers meeting particular resistivity specifications are substantially higher than for p-type wafers; substantially eliminating the cost benefit of the simpler process. Further, it is not entirely clear at the present state of the art that partitions can be successfully formed consistent with this alternative process.